Program control apparatus

ABSTRACT

Program control apparatus for generating programmed control signals comprises a clock pulse oscillator, a frequency divider or multiplier for converting the clock pulse into a plurality of frequency signals of different frequencies, a logical operation circuit for selecting the frequency signals in accordance with a command signal, a counter for counting a preset number of the outputs from the logical operation circuit for successively providing the programmed control signal, and means responsive to each control signal for resetting the counter.

United States Patent Kubo [451 Apr. 18, 1972 [54] PROGRAM CONTROLAPPARATUS R f r i d 72 Inventor: Moritada Kubo, Tokyo, Japan UNITEDSTATES PATENTS [73] Assignee: Tokyo Shibaura Electric Co., Ltd.,2,927,161 3/1960 Harris ..328/ 104 X Ka ,vasaki.shi Japan 2,941, IGOSSlaU 72,994,790 8/1961 Delaney ..328/42 X 1 F1led= 11,197" 3,172,0423/1965 Dawirs ..328/136 x 3,263,174 7/1966 Bjorkman et all........307/271 X [21] 97285 3,264,566 8/1966 Kaufman et a1 ..307/271 x3,500,215 3/1970 Leuthold et a1 ..328/61 {30] Foreign ApplicationPriority Data Primary Examiner-Stanley T. Krawczewicz Dec. 13, 1969Japan ..44/99842 Atwmey ]:|ynn & F i h f Dec. 13, 1969 Japan ..44/99843Dec. 13, 1969 Japan. .....44/99844 [57] ABSTRACT Dec, 13, 1969 Japan.....,44/99845 Program control apparatus for generating programmed com ttrol signals comprises aclock pulse oscillator, a frequency di- [52]U.S. Cl ..328/61, 307/225, 307/271, vider or multiplier for convertingthe clockpulse into a 328/37, 328/38, 328/39, 328/48, 328/104, 328/14rality of frequency signals of different frequencies, a logical [51]IHLCL ..H03k l/00 operation circuit for selecting the frequency signalsin ac- [58] Field of Search ..328/37, 38, 39,40, 41,42, cordance with acommand signal, a counter for counting a preset number of the Outputsfrom the logical operation circuit for successively providing theprogrammed control signal, and means responsive to each control signalfor resetting the counter.

10 Claims, 8 Drawing Figures EFEEJL PATENTEDIPII I8 1972 SHEET 10? 3 I fFREQuE N OSCILLATOR f DIVIDER I I- I i i I i I f COMMAND 5 n SIGNAL I31iii??? LOGICAL OPERATION IRCUIT I4 F SELECTION SIGNAL (b) SELECTION JSIGNAL (C) 0R GATE OUTPUT (d) COUNTER OUTPUT 0 FREQUENCY OSCILLATORDIVIDER 132 3 COMMANDjJ C SIGNAL f f f I i4n 18 E18 I82 181'] SHIFT p17REGISTER 5 COUNTER 'ZE RESET I SIGNAL F l 'G. 1

T3 TIME I? COUNTER OUTPUI RESET SIGNAL PATENTEBAPR 18 I972 3. 657.. 658sum 2 or a FIG. 4

OUTPUT- -T -C=1 f1 V (a) PULSE mm SIGNAL T OUTPUT (b) PULSE I H T W2 4SiGNAL t COMMAND E SIGNAL g COUNTER 5 5P (0) OUTPUT f 2 SIGNAL 1 0 T1T1+T2 TIME 1 FREQUENCY OSCILLATOR DIVIDER C C2 \C4 COMMAND SIGNAL 49SHIFT REGISTER SHIFT REGISTER PAIE'NTEIIIPII 18 I972 OUTPUT PULSE SIGNALOUTPUT PULSE SIGNAL COUNTER OUTPUT COMMAND S IGNAL 3.657.658 SHEET 30F 3FIG. 6

FIG. 7.

FREQUENCY DI VIDER 1 COUNTER f fg RESET f SIGNAL I COMMAND SIGNAL I I TI I I"-I'r SHIFT MATRIX i3 CIRCUIT REGISTER COMMAND SIGNAL 0 FIG.8

FREQUENCY OSCILLATOR MULTIPLIER PROGRAM cosmos APPARATUS This inventionrelates to program control apparatus and more particularly to a programcontrol apparatus wherein a plurality of frequency signals are selectedaccording to a command for causing a single counter of a given capacityto sequentially generate control signals at a desired time according toa prescribed program and is especially useful to be mounted on asatellite and the like space vehicles.

Certain program control apparatus designed to generate control signalsat a definite time interval according to a prescribed program andapplied these control signals to another control device, for example, aprogram control apparatus mounted on a satellite often receives acommand signal from a ground station such that cut off a rocket of apredetermined stage after a predetermined number of seconds.Conventional program control apparatus to be mounted on a satellitegenerally comprises an oscillator for generating clock pulses of adefinite frequency, and a plurality of counters of different number ofcounts respectively counting clock pulses from the oscillatorrespectively through switching devices. Responsive to a command signalsent from a ground station a particular switching device is operated tocause a given counter to count up a predetermined number of clock pulsesfor producing a control signal which is supplied to another controldevice.

As above described, since in the conventional program control apparatus,respective counters have different capacities where the command signalreceived involves a number of different contents it is necessary tomount a plurality of counters for such different contents on a satellitethus increasing the dimension and weight of the program controlapparatus which is of course not desirable for space vehicles.

It is therefore an object of this invention to provide improved programcontrol apparatus according to which various functions provided by aplurality of counters can be afforded by a single counter.

A more specific object of this invention is to provide a program controlapparatus which is compact and light weight and yet can provide.programmed control signals.

SUMMARY OF THE INVENTION According to this invention there is providedprogram control apparatus comprising an oscillator for generating aclock pulse, means for converting the clock pulse into a plurality offrequency signals of different frequencies, program selector means forselecting the frequency signals in accordance with a predeterminedprogrammed order, a shift register for shifting the output from theprogram selector means, a logical operation circuit for effecting alogical operation of the output from the shift register and the outputfrom the program selector means for sequentially producing output pulsesin accordance with the shift pulse from the shift register, a counterfor counting a preset number of the output pulses from the logicaloperation circuit for producing a control output and means responsive tothe control output from the counter for resetting the same whereby toproduce programmed control outputs.

This invention can be more fully understood from the following detaileddescription when taken in connection with the accompanying drawings, inwhich:

FIG. 1 is a block diagram of one embodiment of this invention;

FIG. 2 shows waveforms of pulses to explain the operation of theembodiment shown in FIG. 1;

FIG. 3 is a block diagram of a modified embodiment of this invention;

FIG. 4 shows waveforms of pulses to explain the operation of theembodiment shown in FIG. 3;

FIG. 5 shows-a block diagram of another embodiment of this invention;

FIG. 6 shows waveforms of pulses to explain the operation of theembodiment shown in FIG. 5;

FIG. 7 shows a block diagram of still further modification of thisinvention.

FIG. 8 shows, in part, a modified embodiment of the invention.

A preferred embodiment of this invention diagrammatically shown in FIG.1 comprises an oscillator 11 which produces clock pulse signals of adefinite frequency, a frequency divider 12 for producing a plurality offrequency signals, a logical operation circuit 14 and a plurality ofswitches 13,, 13, 13,,, for example relays, for applying frequencydivided signals to respective input terminals of the logical operationcircuit, which may comprise a plurality of OR gate circuits. The outputs from the logical operation circuit 14 are sent to a counter 15according to a programmed order. When the counter 15 counts up apredetermined number of counts a control signal is supplied to a controldevice, not shown, via an output terminal 16. As shown, this output isfedback to counter 15 to reset it to prepare for the next counting;cycle.

The operation of the embodiment shown in FIG. 1 will now be describedwith reference to FIG. 2. The frequency divider 12 operates to convert aclock pulse of a definite frequency f into pulse signals of difierentfrequencies of k f, k f k,,f, where k,, k k, represent constants. Acommand signal (indicated by an arrow in FIG. 1) operates suitableswitches to supply an appropriate combination of these frequency signalsto the logical operation circuit. Assuming the outputs from frequencydivider l2 to be rectangular waves, by the logical sum of the OR gatecircuits of the logical operation circuit an output is produced having aresultant waveform given by C k, f akm f (1%,. f, where k, and k areconstants and have a relation k, k,,, k,.. Denoting the recurrenceperiod of the rectangular waveform by T and the pulse width by W a isgiven by a T- W/ T and corresponds to the ratio of one period to thelength of the zero line. In other words, the term a shows that thedensity of the pulses can be varied by the suitable selection ofwaveforms of pulses by the command signal. By repeating the countingoperation of a given number of pulses (for example C and then resettingthe counter 15, output pulses P P, can be produced at a definiteinterval according to a prescribed program commanded by the commandsignal. As shown in FIGS. 2a to 2d, when switches 13, and 13,,

' are operated to select only frequency signals/j andfm (shown by FIGS.2a and 2b) among various outputs from the sequescy divider 12 accordingto the programmed command signal, so as'to add these selected signals bythe logical operation circuit 14, as shown by FIG. 2c, the sum issupplied to counter 15. Theneach time the counter counts up the presetnumber of pulses C output pulses p P and P are produced at equalspacings.

Since the number of pulses C to be counted is preset for each counter,the spacing between output pulses At is given by an equation Co Atlkve r'1-fi. f?! fii'i:.;.a The type of freqiincysignalsselectedl isdetermined by the command signal and moreover since constants a and fare predetermined by a particular design it is easy to determine thepulse spacing At required for producing output pulses of equal spacings.

In this manner, the above described embodiment can miniaturize theprogram control apparatus with improved reliability since programmedcontrol output signals of a predetermined spacing can be readilyproduced with a single counter.

A modified embodiment shown in FIG. 3 comprises an oscillator 11, afrequency divider 12, switches 13,, 13, 13,, which are identical tothose shown in FIG. 1, and a logical operation circuit comprised by aplurality of AND gate circuits 14,, 14 14,, respectively connected tothe outputs of the frequency divider through respective switches, theopposite input tenninals of these AND gate circuits being connected tooutput tenninals of a shift register 17. The output terminals of the ANDgate circuits are commonly connected to an input of a counter 15 of apredetermined capacity. Thus, each time the counter counts up a presetnumber of pulses, for example C, a control output signal is provided tooutput terminal 16. Again the output is fed back to the counter to resetthe same. Further, the output at terminal 16 is supplied to the input ofthe shift register 17 to sequentially shift the outputs from the logicaloperation circuit according to a prescribed program.

The operation of the embodiment shown in FIG. 3 will become apparentfrom the following description when taken in conjunction with FIG. 4.More particularly all switches 13,, 13 13,, are closed by a programmedcommand signal. The frequency divider 12 operates to convert each clockpulse of definite frequency f supplied by oscillator 11 into pulsesignals of various frequencies k,f, k f k,,f, which are applied tocorresponding switches 13,, 13 13,,, as above described. Assuming nowthat the first output from shift register 17 is supplied from itsterminal 18,, as both input terminals of AND gate circuit 14 aresupplied with input signals, this AND gate circuit is enabled to supplyto counter 15 an output pulse signal (FIG. 4a) of a frequency equal tothat of the signal supplied through switch 13 Then the counter countspulses of a number C If, until a time t, is reached starting from theoperation commencing point 0. When the counter counts up this number, itwill supply an output signal P, (see FIG. 4c) to output terminal 16which is also used to reset counter 15 and shift the output of shiftregister 17 to its output terminal 18 Then AND gate circuit 14 isdisabled and AND gate circuit 14 is enabled to supply an output pulsesignal (FIG. 4b) having the same frequency as the signal through switch13 to counter 15 which counts a number of pulses C t f until time twhich is later than 1 When counter 15 counts up this preset number ofpulses, an output signal P (FIG. 40) is applied to output terminal 16which is also used to reset counter 15 and shift the output of shiftregister 17 to terminal 18 By repeating the above described cycles forsequentially shifting output terminals of shift register 17, programmedoutput pulse signals P P P,, can be produced at a definite interval,which may be varied in any desired manner by varying the frequency ofthe output pulses of the frequency divider 12.

Another embodiment shown in FIG. is generally identical to that shown inFIG. 3 except that output control signals from the counter are suppliedto corresponding AND gate circuits 19,, 19 19,, comprising a secondlogical operation circuit and that the order of outputs from these ANDgate circuits are shifted by a second shift register 21, so thatcorresponding elements of these two embodiments are designated by thesame reference numerals.

Thus, when the first shift register 17 provides its output on terminal18,, AND gate circuit 14, is enabled to supply an output pulse signal(FIG. 6a) having the same frequency as the signal through switch 13, tocounter 15. When the second shift register 21 provides its output on thefirst terminal 22,, the counter counts a number of pulses C t f, sentfrom AND gate circuit 14, for an interval t When the counter counts upthis preset number, it supplies a pulse signal to one input terminal ofAND gate circuit 19,. Then this AND gate circuit is enabled by theinputs impressed upon its both input terminals to provide an outputpulse P (FIG. 6c) for output terminal 16. As before, this output pulse Pis also utilized to shift the output of the first shift register 17 fromterminal 18 to terminal 18 to shift the output of the second shiftregister 21 from terminal 22, to terminal 22 and to reset counter 15.Then AND gate circuit 14 is enabled to supply to counter 15 a pulsesignal (FIG. 6b) which is supplied through switch 13 and has a frequencydifferent from that of the pulse signal supplied through switch 13,.Since, the second shift register 21 now provides its output on terminal222, the counter 15 counts the second preset number of pulses C If, foran interval When counter 15 counts up this second preset number, itprovides a pulse signal to one input of AND gate circuit 19 Since bothinputs are energized, AND gate circuit 19 is enabled to supply an outputsignal P (FIG. 6c) to output terminal 16. This output signal P, shiftsthe output of the first shift register 17 from terminal 18 to terminal18 and shifts the output of the second shift register 21 from terminal22 to terminal 22 Further, this output signal P resets counter 15. Theseoperations are sequentially repeated until finally the last presetnumber C t fl, is counted to produce an output signal P,,.

In this manner, programmed output signals of desired periods, that isoutput signals P P P are produced at intervals t t t,, which satisfy therelations C=t f C f, C t,,f,, by setting counter 15 to various presetcounts C C, C,,. In other words, intervals t,, t, t,, may be varied toany desired values by suitable selection of the preset count C, andfrequency f} Although in the embodiment shown in FIG. 3, the outputs offrequency divider 12 are selected by a programmed command signal appliedto switches 13,, 13 13,,, in another embodiment shown in FIG. 7, theoutputs of the frequency divider 12 are applied to terminals ofcorresponding rows or columns of a matrix circuit 13 whereas programmedcommand signals are applied to the columns or rows of the matrix circuitso as to determine the order of deriving out of the outputs from thefrequency divider 12. The outputs from the matrix circuit are suppliedto counter 15 through a logical operation circuit 14 comprising aplurality of AND gate circuits 14 14 14, so as to produce output controlsignals.

In operation, two types of the command signals are applied to matrixcircuit 13 to selectively determine the order of deriving out offrequency signals f,, f, f, from the frequency divider 12. Such ordercan be selected arbitrarily. For example, the signal of frequency f maybe supplied to AND gate circuit 14 and signals of frequencies f f 14,,,respectively, for the purpose of selecting an order of fyf f,,n. Asabove described, since frequency signals f f f, formed by frequencydivider 12 are impressed upon respective input terminals of matrixcircuit 13 when the output of the shift register 17 firstly appears onits terminal 18 both input terminals of AND gate circuit 14, will beenergized thus enabling the same. Thus, a signal having frequency f issupplied to counter 15 which counts a preset number of pulses C t,f, aninterval When the counter 15 counts up this preset number, it providesan output signal P, to output terminal 16. Again, this output signal isutilized to reset a counter 15 and to shift the output of shift register17 to terminal 18,. Then. AND gate circuit 14, is disabled whereas ANDgate circuit 14 is enabled to supply the signal of frequency f, tocounter 15, which when counts up another preset number of pulses C 2,for an interval t, provides an output signal P for output terminal 16.Thus counter 15 is reset and shift register 17 is shifted to its outputterminal 18 Thereafter the same operation is repeated for signals offrequencies f;, f,,. In this manner, programmed output pulses P P P, areproduced with predetermined intervals.

Although in each of the embodiments shown in FIGS. 1, 3, 5 and 7, afrequency divider 12 was used to derive a plurality of frequency signalsfrom a clock pulse of an oscillator 11 it will be clear that a frequencymultiplier can also be used. Such an arrangement is shown in FIG. 8,wherein an oscillator 1 1 is coupled to a multiplier 20 to provideoutput frequencies analogous to the outputs of the dividers of FIGS. 1,3, 5 and 7.

Furthermore, it will be apparent that the invention is not limited toprogram control apparatus adapted to be mounted on space vehicles whichare operated by command signals sent from a ground station and that theprogram control apparatus may be used in any applications where it isnecessary to produce signals at a predetermined interval.

What is claimed is:

1. A program control apparatus comprising an oscillator for generating aclock pulse, means for converting said clock pulse into a plurality offrequency signals of different frequencies, program selector means forselecting said frequency signals in accordance with a predeterminedprogrammed order, a shift register for shifting the output from saidprogram selector means, a logical operation circuit for effecting alogical operation of the output from said shift register and the outputfrom said program selector means for sequentially producing outputpulses in accordance with the shift pulse from said shift register, acounter for counting a preset number of the output pulses from saidlogical operation circuit for producing a control output and meansresponsive to said control output from said counter for resetting thesame, whereby to produce programmed control outputs.

2. A program control apparatus according to claim 1 wherein said meansfor producing said plurality of frequency signals comprises a frequencydivider.

3. A program control apparatus according to claim 1 wherein said meansfor producing said plurality of frequency signals comprises a frequencymultiplier.

4. A program control apparatus according to claim 1 wherein said programselector means comprises a plurality of switching means of a numbercorresponding to the number of said frequency signals, said switchingmeans being operated by a command signal.

5. A program control apparatus according to claim 1 wherein said programselector means comprises a matrix circuit, input terminals of the rowsor columns of said matrix circuit are connected to receive saidplurality of frequency signals whereas the input tenninals of thecolumns or rows of said matrix circuit are connected to receive twotypes of command signals to change the order of outputs from said matrixcircuit.

6. A program control apparatus according to claim 1 wherein said logicaloperation circuit comprises a plurality of OR gate circuits forselecting either one of a plurality of output pulses for producingprogrammed outputs.

7. A program control apparatus according to claim 1 wherein said logicaloperation circuit comprises a plurality of AND gate circuits of thenumber corresponding to the number of preset counts of said counter, oneinput terminal of each AND gate circuit is connected to a correspondingone output terminal of said program selector circuit whereas the otherinput terminal is connected to a corresponding one output terminal ofsaid shift register and wherein output terminals of said AND gatecircuits are commonly connected to an output terminal of the controloutput signal.

8. A program control apparatus according to claim 1 which furtherincludes means responsive to the output signal from said logicaloperation circuit for shifting said shift register.

9. A program control apparatus comprising an oscillator for generating aclock pulse, means for converting said clock pulse into a plurality offrequency signals of different frequencies, program se ector means forselecting said frequency signals in accordance with a predeterminedprogrammed order, a first shift register for shifting the output fromsaid program selector means, a first logical operation circuit foreffecting a logical operation of the output from said shift register andthe output from said program selector means for sequentially producingoutput pulses in accordance with the shift pulse from said shiftregister, a counter for counting a preset number of the output pulsesfrom said first logical operation circuit to produce an output, a secondshift register for shifting the output from said counter, a secondlogical operation circuit for effecting a logical operation of theoutput from said second shift register and the output from said counterfor sequentially producing output pulses in accordance with the shiftpulse from said second shift register, and means responsive to theoutput pulse from said second logical operation circuit for resettingsaid counter.

10. A program control apparatus comprising an oscillator for generatinga clock pulse, means for converting said clock pulse into a plurality offrequency signals of different frequencies, program selecting means forselecting said frequency signals in accordance with a predeterminedprogrammed order, a logical operation circuit for successively sendingout the outputs from said program selector means in accordance with aprogrammed order, a counter for counting up preset number of the outputsfrom said logical operation circuit so as to produce an output, andmeans responsive to each output of said counter for resetting the same.

1. A program control apparatus comprising an oscillator for generating aclock pulse, means for converting said clock pulse into a plurality offrequency signals of different frequencies, program selector means forselecting said frequency signals in accordance with a predeterminedprogrammed order, a shift register for shifting the output from saidprogram selector means, a logical operation circuit for effecting alogical operation of the output from said shift register and the outputfrom said program selector means for sequentially producing outputpulses in accordance wiTh the shift pulse from said shift register, acounter for counting a preset number of the output pulses from saidlogical operation circuit for producing a control output and meansresponsive to said control output from said counter for resetting thesame, whereby to produce programmed control outputs.
 2. A programcontrol apparatus according to claim 1 wherein said means for producingsaid plurality of frequency signals comprises a frequency divider.
 3. Aprogram control apparatus according to claim 1 wherein said means forproducing said plurality of frequency signals comprises a frequencymultiplier.
 4. A program control apparatus according to claim 1 whereinsaid program selector means comprises a plurality of switching means ofa number corresponding to the number of said frequency signals, saidswitching means being operated by a command signal.
 5. A program controlapparatus according to claim 1 wherein said program selector meanscomprises a matrix circuit, input terminals of the rows or columns ofsaid matrix circuit are connected to receive said plurality of frequencysignals whereas the input terminals of the columns or rows of saidmatrix circuit are connected to receive two types of command signals tochange the order of outputs from said matrix circuit.
 6. A programcontrol apparatus according to claim 1 wherein said logical operationcircuit comprises a plurality of OR gate circuits for selecting eitherone of a plurality of output pulses for producing programmed outputs. 7.A program control apparatus according to claim 1 wherein said logicaloperation circuit comprises a plurality of AND gate circuits of thenumber corresponding to the number of preset counts of said counter, oneinput terminal of each AND gate circuit is connected to a correspondingone output terminal of said program selector circuit whereas the otherinput terminal is connected to a corresponding one output terminal ofsaid shift register and wherein output terminals of said AND gatecircuits are commonly connected to an output terminal of the controloutput signal.
 8. A program control apparatus according to claim 1 whichfurther includes means responsive to the output signal from said logicaloperation circuit for shifting said shift register.
 9. A program controlapparatus comprising an oscillator for generating a clock pulse, meansfor converting said clock pulse into a plurality of frequency signals ofdifferent frequencies, program selector means for selecting saidfrequency signals in accordance with a predetermined programmed order, afirst shift register for shifting the output from said program selectormeans, a first logical operation circuit for effecting a logicaloperation of the output from said shift register and the output fromsaid program selector means for sequentially producing output pulses inaccordance with the shift pulse from said shift register, a counter forcounting a preset number of the output pulses from said first logicaloperation circuit to produce an output, a second shift register forshifting the output from said counter, a second logical operationcircuit for effecting a logical operation of the output from said secondshift register and the output from said counter for sequentiallyproducing output pulses in accordance with the shift pulse from saidsecond shift register, and means responsive to the output pulse fromsaid second logical operation circuit for resetting said counter.
 10. Aprogram control apparatus comprising an oscillator for generating aclock pulse, means for converting said clock pulse into a plurality offrequency signals of different frequencies, program selecting means forselecting said frequency signals in accordance with a predeterminedprogrammed order, a logical operation circuit for successively sendingout the outputs from said program selector means in accordance with aprogrammed order, a counter for counting up preset number of the outputsfrom said logical operation circuit so as to produCe an output, andmeans responsive to each output of said counter for resetting the same.